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preliminary cy62167g/cy62167ge mobl ? 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-81537 rev. *i revised september 18, 2014 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc) features ultra-low standby current ? typical standby current: 4.6 ? a ? maximum standby current: 16 ? a high speed: 45 ns / 55 ns embedded error-correcting code (ecc) for single-bit error correction wide voltage range: 1.65 v to 2.2 v, 2.2 v to 3.6 v, and 4.5 v to 5.5 v 1.0-v data retention transistor-transistor logic (ttl) compatible inputs and outputs error indication (err) pin to indicate 1-bit error detection and correction 48-pin tsop i package configurable as 1 m 16 or 2 m 8 sram available in pb-free 48-ball vfbga and 48-pin tsop i packages functional description cy62167g and cy62167ge are high-performance cmos, low-power (mobl ? ) sram devices with embedded ecc [1] . both devices are offered in single and dual chip enable options and in multiple pin configurations. th e cy62167ge device includes an err pin that signals a single-bit error-detection and correction event during a read cycle. to access devices with a single chip enable input, assert the chip enable (ce ) input low. to access dual chip enable devices, assert both chip enable inputs ? ce 1 as low and ce 2 as high. to perform data writes, assert the write enable (we ) input low, and provide the data and address on the device data pins (i/o 0 through i/o 15 ) and address pins (a 0 through a 19 ) respectively. the byte high enable (bhe) and byte low enable (ble ) inputs control byte writes and write data on the corresponding i/o lines to the memory location specified. bhe controls i/o 8 through i/o 15 and ble controls i/o 0 through i/o 7 . to perform data reads, assert the output enable (oe ) input and provide the required address on the address lines. you can access read data on the i/o lines (i/o 0 through i/o 15 ). to perform byte accesses, assert the required byte enable signal (bhe or ble ) to read either the upper byte or the lower byte of data from the specified address location. all i/os (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high for a single chip enable device and ce 1 high / ce 2 low for a dual chip enable device), or the control signals are de-asserted (oe , ble , bhe ). these devices have a unique byte power-down feature where, if both the byte enables (bhe and ble ) are disabled, the devices seamlessly switch to t he standby mode irrespective of the state of the chip enables, thereby saving power. on the cy62167ge devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the err output (err = high). see the truth table ? cy62167g/cy62167ge on page 17 for a complete description of read and write modes. the cy62167g and cy62167ge devices are available in a pb-free 48-pin tsop i package and 48-ball vfbga packages. the logic block diagrams are on page 2. the device in the 48-pin tsop i package can also be configured to function as a 2 m words 8 bit device. refer to the pin configurations section for details. note 1. this device does not support au tomatic write-back on error detection.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 2 of 28 1m x 16 / 2m x 8 ram array row decoder a1 a2 a3 a4 a5 a6 a7 a8 a9 a0 column decoder a10 sense amps ecc decode a11 a12 a13 a14 a15 a16 a17 a18 a19 ecc encode data in drivers i/o 0 -i/o 7 i/o 8 -i/o 15 bhe we oe ble ce 2 ce 1 byte power down circuit ce bhe ble logic block diagram ? cy62167g 1m x 16 / 2m x 8 ram array row decoder a1 a2 a3 a4 a5 a6 a7 a8 a9 a0 column decoder a10 sense amps ecc decode a11 a12 a13 a14 a15 a16 a17 a18 a19 ecc encode data in drivers i/o 0 -i/o 7 i/o 8 -i/o 15 bhe we oe ble ce 2 ce 1 byte power down circuit ce bhe ble err logic block diag ram ? cy62167ge
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 3 of 28 contents pin configuration ? cy62167g ... .............. .............. ......... 4 pin configuration ? cy62167ge .............. .............. ......... 5 product portfolio .............................................................. 7 maximum ratings ............................................................. 8 operating range ............................................................... 8 dc electrical characteristics .......................................... 8 capacitance .................................................................... 10 thermal resistance ........................................................ 10 ac test loads and waveforms ..................................... 10 data retention characteristics ..................................... 11 data retention waveform .............................................. 11 switching characteristics .............................................. 12 switching waveforms .................................................... 13 truth table ? cy62167g/cy62167ge ............... ............ 17 err output ? cy62167ge ............................................. 17 ordering information ...................................................... 18 ordering code definitions ......................................... 18 package diagrams .......................................................... 19 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 errata ............................................................................... 22 part numbers affected .............................................. 22 cy62167g(e) qualification stat us .............. .............. 22 cy62167g(e) sram errata su mmary ....... .............. 22 document history page ................................................. 24 sales, solutions, and legal information ...................... 28 worldwide sales and design s upport ......... .............. 28 products .................................................................... 28 psoc? solutions ...................................................... 28 cypress developer community ................................. 28 technical support ................. .................................... 28
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 4 of 28 pin configuration ? cy62167g figure 1. 48-ball vfbga pinout (dua l chip enable without err) ? cy62167g [2] figure 2. 48-pin tsop i pinout (dual chip enable without err) ? cy62167g [2, 3] we a 11 a 10 a 6 a 0 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce 2 nc bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce 1 a0 notes 2. nc pins are not connected internally to the die and are typi cally used for address expansion to a higher-density device. refe r to the respective datasheets for pin configuration. 3. tie the byte pin in the 48-pin tsop i package to v cc to use the device as a 1 m 16 sram. the 48-pin ts op i package can also be used as a 2 m 8 sram by tying the byte signal to v ss . in the 2 m 8 configuration, pin 45 is the extra address line a20, while bhe , ble, and i/o 8 to i/o 14 pins are not used and can be left floating.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 5 of 28 pin configuration ? cy62167ge figure 3. 48-ball vfbga pinout (single chip enable with err) ? cy62167ge [4] figure 4. 48-ball vfbga pinout (dual chip enable with err) ? cy62167ge [4] we a 11 a 10 a 6 a 0 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe err a 17 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc a 1 a 2 a 3 we a 11 a 10 a 6 a 0 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 err v cc a 1 a 2 a 3 note 4. nc pins are not connected internally to the die and are typi cally used for address expansion to a higher-density device. refe r to the respective datasheets for pin configuration.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 6 of 28 figure 5. 48-pin tsop i pinout (dual chip enable with err) ? cy62167ge [5, 6] pin configuration ? cy62167ge (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce 2 err bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce 1 a0 notes 5. nc pins are not connected internally to the die and are typi cally used for address expansion to a higher density device. refe r to the respective datasheets for pin configuration. 6. tie the byte pin in the 48-pin tsop i package to v cc to use the device as a 1 m 16 sram. the 48-pin tsop i package can also be used as a 2 m 8 sram by tying the byte signal to v ss . in the 2 m 8 configuration, pin 45 is the extra address line a20, while the bhe , ble, and i/o 8 to i/o 14 pins are not used and can be left floating.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 7 of 28 product portfolio product features and options (see the pin configurations section) range v cc range (v) speed (ns) current consumption operating i cc , (ma) standby, i sb2 ( a) f = f max typ [7] max typ [7] max cy62167g(e)18 single or dual chip enables optional err pin industrial 1.65 v?2.2 v 55 29 32 5.5 26 cy62167g(e)30 2.2 v?3.6 v 45 29 36 4.6 16 cy62167g(e) 4.5 v?5.5 v note 7. typical values are included only for reference and are not guaranteed or tested. typical values are measured at v cc = 1.8 v (for v cc range of 1.65 v?2.2 v), v cc =3v (for v cc range of 2.2 v?3.6 v), and v cc = 5 v (for v cc range of 4.5 v?5.5 v), t a = 25 c.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 8 of 28 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential .................................... ........................?0.5 v to 6 v dc voltage applied to outputs in high z state [8] .................................. ?0.5 v to v cc + 0.5 v dc input voltage [8] .............................. ?0.5 v to v cc + 0.5 v output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................. >2001 v latch-up current ..................................................... >140 ma operating range grade ambient temperature v cc [9] industrial ?40 ? c to +85 ? c 1.65 v to 2.2 v, 2.2 v to 3.6 v, 4.5 v to 5.5 v dc electrical characteristics over the operating range of ?40 ? c to 85 ? c parameter description test conditions 45/55 ns unit min typ [10] max v oh output high voltage 1.65 v to 2.2 v v cc = min, i oh = ?0.1 ma 1.4 ? ? v 2.2 v to 2.7 v v cc = min, i oh = ?0.1 ma 2.0 ? ? 2.7 v to 3.6 v v cc = min, i oh = ?1.0 ma 2.2 ? ? 4.5 v to 5.5 v v cc = min, i oh = ?1.0 ma 2.4 ? ? v ol output low voltage 1.65 v to 2.2 v v cc = min, i ol = 0.1 ma ? ? 0.2 v 2.2 v to 2.7 v v cc = min, i ol = 0.1 ma ? ? 0.4 2.7 v to 3.6 v v cc = min, i ol = 2.1 ma ? ? 0.4 4.5 v to 5.5 v v cc = min, i ol = 2.1 ma ? ? 0.4 v ih input high voltage [8] 1.65 v to 2.2 v ? 1.4 ? v cc + 0.2 v 2.2 v to 2.7 v ? 2.0 ? v cc + 0.3 2.7 v to 3.6 v ? 2.0 ? v cc + 0.3 4.5 v to 5.5 v ? 2.2 ? v cc + 0.5 v il input low voltage [8] 1.65 v to 2.2 v ? ?0.2 ? 0.4 v 2.2 v to 2.7 v ? ?0.3 ? 0.6 2.7 v to 3.6 v ? ?0.3 ? 0.8 4.5 v to 5.5 v ? ?0.5 ? 0.8 i ix input leakage current gnd < v in < v cc ?1.0 ? +1.0 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1.0 ? +1.0 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, cmos levels f = 22.22 mhz (45 ns) ?29.0 36.0ma f = 18.18 mhz (55 ns) ?29.0 32.0ma f = 1 mhz ? 7.0 9.0 ma notes 8. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 2 ns. 9. full device ac operation assumes a 100-s ramp time from 0 to v cc (min) and 200-s wait time after v cc stabilizes to its operational value. 10. indicates the value for the center of distribution at 3.0 v, 25 c and not 100% tested.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 9 of 28 i sb1 [11] automatic power down current ? cmos inputs; v cc = 2.2 to 3.6 v and 4.5 to 5.5 v ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , and we ), v cc = v cc(max) ?4.6 16.0 ? a automatic power down current ? cmos inputs v cc = 1.65 to 2.2 v ?5.5 26.0 i sb2 [11] automatic power down current ? cmos inputs v cc = 2.2 to 3.6 v and 4.5 to 5.5 v ce 1 > v cc ? 0.2v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) 25 c ? 4.6 6.0 [12] ? a 40 c ? 5.1 8.0 [12] 70 c ? 8.4 12.0 [12] 85 c ? 12.0 16.0 automatic power down current ? cmos inputs v cc = 1.65 to 2.2 v ce 1 > v cc ? 0.2v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?5.5 26.0 dc electrical characteristics (continued) over the operating range of ?40 ? c to 85 ? c parameter description test conditions 45/55 ns unit min typ [10] max notes 11. chip enables (ce 1 and ce 2 ) and byte must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 12. the i sb2 maximum limits at 25 c, 40 c, and 70 c are guaranteed by design and not 100% tested.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 10 of 28 capacitance parameter [13] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [13] description test conditions 48-ball vfbga 48-pin tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 31.50 57.99 c/w ? jc thermal resistance (junction to case) 15.75 13.42 c/w ac test loads and waveforms figure 6. ac test loads and waveforms v high v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v cc equivalent to: thvenin equivalent all input pulses r th r1 parameters 1.8 v 2.5 v 3.0 v 5.0 v unit r1 13500 16667 1103 1800 ? r2 10800 15385 1554 990 ? r th 6000 8000 645 639 ? v th 0.80 1.20 1.75 1.77 v note 13. tested initially and after any design or process changes that may affect these parameters.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 11 of 28 data retention characteristics over the operating range parameter description conditions min typ [14] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [15, 16] data retention current 1.2 v < v cc < 2.2 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ? 5.5 26.0 ? a 2.2 v < v cc < 3.6 v or 4.5 v < v cc < 5.5 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ? 4.6 16.0 ? a t cdr [17] chip deselect to data retention time 0??? t r [18] operation recovery time 45/55 ? ? ns data retention waveform figure 7. data retention waveform [19] t cdr t r v dr ? = ? 1.0 ? v data ? retention ? mode v cc ? (min) v cc ? (min) v cc ce 2 ce 1 ? or ? bhe. ? ble notes 14. indicates the value for the center of distribution at 3.0 v, 25 c and not 100% tested. 15. chip enables (ce 1 and ce 2 ) and byte must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 16. i ccdr is guaranteed only after the device is first powered up to v cc (min) and then brought down to v dr . 17. tested initially and after any design or proce ss changes that may affect these parameters. 18. full-device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 19. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble .
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 12 of 28 switching characteristics parameter [20, 21] description 45 ns 55 ns unit min max min max read cycle t rc read cycle time 45.0 ? 55.0 ? ns t aa address to data valid / address to err valid ? 45.0 ? 55.0 ns t oha data hold from address change / err hold from address change 10.0 ? 10.0 ? ns t ace ce 1 low and ce 2 high to data valid / ce low to err valid ? 45.0 ? 55.0 ns t doe oe low to data valid / oe low to err valid ? 22.0 ? 25.0 ns t lzoe oe low to low-z [21] 5.0 ? 5.0 ? ns t hzoe oe high to high-z [21, 22] ? 18.0 ? 18.0 ns t lzce ce 1 low and ce 2 high to low-z [21] 10.0 ? 10.0 ? ns t hzce ce 1 high and ce 2 low to high-z [21, 22] ? 18.0 ? 18.0 ns t pu ce 1 low and ce 2 high to power-up 0 ? 0 ? ns t pd ce 1 high and ce 2 low to power-down ? 45.0 ? 55.0 ns t dbe ble / bhe low to data valid ? 45.0 ? 55.0 ns t lzbe ble / bhe low to low-z [21] 5.0 ? 5.0 ? ns t hzbe ble / bhe high to high-z [21, 22] ? 18.0 ? 18.0 ns write cycle [23, 24] t wc write cycle time 45.0 ? 55.0 ? ns t sce ce 1 low and ce 2 high to write end 35.0 ? 40.0 ? ns t aw address setup to write end 35.0 ? 40.0 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 35.0 ? 40.0 ? ns t bw ble / bhe low to write end 35.0 ? 40.0 ? ns t sd data setup to write end 25.0 ? 25.0 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high-z [21, 22] ? 18.0 ? 20.0 ns t lzwe we high to low-z [21] 10.0 ? 10.0 ? ns notes 20. test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 v (for v cc > 3 v) and v cc /2 (for v cc < 3 v), and input pulse levels of 0 to 3 v (for v cc > 3 v) and 0 to v cc (for v cc < 3v). test conditions for the read cycle use the output loading shown in figure 6 on page 10 , unless specified otherwise. 21. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 22. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 23. the internal write time of the memory is defined by the overlap of we = v il , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must refer to th e edge of the signal that terminates the write. 24. the minimum write cycle pulse width for write cycle 1 (we controlled, oe low) should be equal to the sum of t hzwe and t sd
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 13 of 28 switching waveforms figure 8. read cycle no. 1 of cy 62167g (address transition controlled) [25, 26] figure 9. read cycle no. 1 of cy62167ge (address transition controlled) [25, 26] address data i/o previous data out valid data out valid t rc t oha t aa address data i/o previous ? data out ? valid data out ? valid t rc t oha t aa err previous ? err ? valid err ? valid t oha t aa notes 25. the device is continuously selected. oe = v il , ce = v il , bhe or ble , or both = v il . 26. we is high for read cycle.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 14 of 28 figure 10. read cycle no. 2 (oe controlled) [27, 28, 29, 31] figure 11. write cycle no. 1 (we controlled, oe low) [28, 30, 31, 33] switching waveforms (continued) t rc t hzce t pd t ace t doe t lzoe t dbe t lzbe t lzce t pu high impedance data out valid high impedance address ce oe bhe/ ble data i/o v cc supply current t hzoe t hzbe i sb address ce data i/o t wc t sce t hd t sd t bw bhe/ ble t aw t ha t sa t pwe t lzwe t hzwe we data in valid note 32 notes 27. we is high for read cycle. 28. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 29. address valid prior to or coincident with ce low transition. 30. the internal write time of the memory is defined by the overlap of we = v il , ce 1 = v il , bhe or ble , or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must refer to th e edge of the signal that terminates the write. 31. data i/o is in the high-impedance state if ce = v ih , or oe = v ih , or bhe , and/or ble = v ih . 32. during this period, the i/os are in the output state. do not apply input signals. 33. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd .
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 15 of 28 figure 12. write cycle no. 2 (ce controlled) [34, 35, 36] switching waveforms (continued) address ce we bhe/ ble data i/o oe t wc t sce t aw t sa t pwe t ha t bw t hd t hzoe t sd data in valid note 37 notes 34. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 35. the internal write time of the memory is defined by the overlap of we = v il , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminat e a write by going inactive. the data input setup and hold timing must refer to th e edge of the signal that terminates the write. 36. data i/o is in the high-impedance state if ce = v ih , or oe = v ih , or bhe , and/or ble = v ih . 37. during this period, the i/os are in output state. do not apply input signals.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 16 of 28 figure 13. write cycle no. 4 (bhe /ble controlled, oe low) [38, 39, 40] figure 14. write cycle no. 5 (we controlled) [38, 39, 40] switching waveforms (continued) data in valid address ce we data i/o t wc t sce t aw t sa t bw t ha t hd t hzwe t sd bhe/ ble t pwe t lzwe note 41 notes 38. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 39. the internal write time of the memory is defined by the overlap of we = v il , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminat e a write by going inactive. the data input setup and hold timing must refer to th e edge of the signal that terminates the write. 40. data i/o is in the high-impedance state if ce = v ih , or oe = v ih , or bhe , and/or ble = v ih . 41. during this period, the i/os are in output state. do not apply input signals. address ce we bhe/ble data i/o oe t wc t sce t aw t sa t pw e t ha t bw t hd t hzoe t sd data in ? valid note 41
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 17 of 28 truth table ? cy62167g/cy62167ge byte [42] ce 1 ce 2 we oe bhe ble inputs/outputs mode power configuration x [43] hx [43] x x x x high-z deselect/power-down standby (i sb ) 2 m 8 / 1 m 16 xx [43] l x x x x high-z deselect/power-down standby (i sb ) 2 m 8 / 1 m 16 xx [43] x [43] x x h h high-z deselect/power-down standby (i sb ) 1 m 16 h l h h l l l data out (i/o 0 ?i/o 15 )read active (i cc ) 1 m 16 h l h h l h l data out (i/o 0 ?i/o 7 ); high-z (i/o 8 ?i/o 15 ) read active (i cc ) 1 m 16 h l h h l l h high z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) 1 m 16 h l h h h l h high-z output disabled active (i cc ) 1 m 16 h l h h h h l high-z output disabled active (i cc ) 1 m 16 h l h h h l l high-z output disabled active (i cc ) 1 m 16 h l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) 1 m 16 h l h l x h l data in (i/o 0 ?i/o 7 ); high-z (i/o 8 ?i/o 15 ) write active (i cc ) 1 m 16 hlhlxlhhigh-z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) 1 m 16 l l h h l x x data out (i/o 0 ?i/o 7 )readactive (i cc )2 m 8 l l h h h x x high-z output disabled active (i cc )2 m 8 l l h l x x x data in (i/o 0 ?i/o 7 ) write active (i cc )2 m 8 err output ? cy62167ge output mode 0 read operation, no single-bit error in the stored data. 1 read operation, single-bit error detected and corrected. high-z device deselected / outputs disabled / write operation notes 42. this pin is available only in the 48-pin tsop i package. tie the byte to v cc to configure the device in the 1 m 16 option. the 48-pin tsop i package can also be used as a 2 m 8 sram by tying the byte signal to v ss . 43. the ?x? (don?t care) state for the chip enables refer to the logic state (either high or low). intermediate voltage levels o n these pins is not permitted.
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 18 of 28 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 cy62167g30-45bvxi 51-85150 48-ball vf bga (6 8 1 mm) (pb-free), package code: bz48, dual chip enable without err industrial cy62167g30-45zxi 51-85183 48-pin tsop i (12 18.4 1 mm) (pb-free), package code: z48a, dual chip enable without err cy62167g-45zxi 51-85183 48-pin tsop i (12 18.4 1 mm) (pb-free), dual chip enable without err cy62167ge30-45bvxi 51-85150 48-ball vfbga (6 8 1 mm) (pb-free), dual chip enable with err output at pin e3 cy62167ge30-45zxi 51-85183 48-pin tsop i (12 18.4 1 mm) (pb-free), dual chip enable with err output at pin 13 cy62167ge-45zxi 51-85183 48-pin tsop i (12 18.4 1 mm) (pb-free), dual chip enable with err output at pin 13 55 cy62167g18-55bvxi 51-85150 48-ball vf bga (6 8 1 mm) (pb-free), dual chip enable without err industrial cy62167ge18-55bvxi 51-85150 48-ball vfbga (6 8 1 mm) (pb-free), dual chip enable with err output at pin e3 temperature grade: x = i i = industrial pb-free x = blank or 1 blank = dual chip enable; 1 = single chip enable package type: xx = bv or z bv = 48-ball vfbga z = 48-pin tsop i speed grade: xx: 45 = 45 ns and 55 = 55ns voltage range: 30 = 3-v typ; 18 = 1.8-v typ; no character = 5-v typ err output: single-bit e rror correction indicator process technology: g = 65 nm bus width: 7 = 16 density: 6 = 16-mbit family code: mobl sram family company id: cy = cypress cy xx xx 621 6 7 g x - x xx e x
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 19 of 28 package diagrams figure 15. 48-ball vfbga (6 8 1.0 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 20 of 28 figure 16. 48-pin tsop i (12 18.4 1. 0 mm) z48a package outline, 51-85183 package diagrams (continued) 51-85183 *c
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 21 of 28 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine-pit ch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad v volt w watt
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 22 of 28 errata this errata is applicable for the rev. *c silicon only. this section describes the errata for the 16-mbit asynchr onous mobl sram - cy62167g/cy62167ge - in the 65-nm process technology. details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicabilit y. if you have questions, contact your local cypress sales representative or raise a technical support case at www.cypress.com/go/support . part numbers affected cy62167g(e) qualification status product status: engineering samples ( note: reliability qualification is not complete. these samples are recommended to be used for engineering builds and evaluation only, and not for production builds). cy62167g(e) sram errata summary this table defines the errata applicability to available 16-mbit devices. 1. i sb1, i sb2 (standby current) and i ccdr (data retention current) issue problem definition i sb1 (f = fmax), i sb2 (f = 0) and i ccdr do not meet the datasheet limits as captured in the tables below. part number device characteristics cy62167g (all packages and options) cy62167ge (all packages and options) 16-mbit mobl sram items part numbers silicon revision fix status [1] i sb1 , i sb2 and i ccdr (standby current specifications) do not meet datasheet spec cy62167g/ cy62167ge *c fixed devices available from december 14, 2014 parameter description test conditions datasheet errata unit typ [14] typ [14] i sb2 [11] automatic power down current ? cmos inputs v cc = 2.2 to 3.6 v and 4.5 to 5.5 v ce 1 > v cc ? 0.2v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) 25 c 4.6 5.3 ? a 40 c 5.1 5.8 70 c 8.4 9.0 automatic power down current ? cmos inputs v cc = 1.65 to 2.2 v ce 1 > v cc ? 0.2v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) 5.5 6.9
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 23 of 28 parameters affected standby current specifications i sb1 , i sb2 and i ccdr trigger condition when chip enable (s) is/are de-asserted to place the device in standby mode, the current drawn (i sb1 / i sb2) are greater than the datasheet-specified limit. when chip is in data retention mode, the current drawn (i ccdr ) is greater than the datasheet-specified limit. scope of impact since these are engineering samples and are expected to be used for evaluation, a marginal increase in standby/ data retention current is not expected to have an impact. increase in standby/ data retention currents could result in a long term effect of r educed battery life; however, since these are engineering samples expe cted to be used for engineering builds and evaluation only, impa ct is expected to be minimal. workaround ensure adequate source of power that accounts for the increased standby current fix status fixed devices available from december 14, 2014. parameter description test conditions datasheet errata unit typ [14] typ [14] i sb1 [11] automatic power down current ? cmos inputs; v cc = 2.2 to 3.6 v and 4.5 to 5.5 v ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , and we ), v cc = v cc(max) 4.6 5.3 ? a automatic power down current ? cmos inputs v cc = 1.65 to 2.2 v 5.5 6.9 i ccdr [15,16] data retention current 1.2 v < v cc < 2.2 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v 5.5 6.9 ? a 2.2 v < v cc < 3.6 v or 4.5 v < v cc < 5.5 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v 4.6 5.3
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 24 of 28 document history page document title: cy62167g/cy62167ge mobl ? , 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc) document number: 001-81537 rev. ecn no. orig. of change submission date description of change ** 3690096 tava 07/26/2012 new data sheet. *a 3776318 aju 10/30/2012 updated document title to ?16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc)?. updated features (included ecc feature, updated typical standby current spec). added note #1 corrected typos in functional description . updated logic block diagram ? cy62167g , logic block diagram ? cy62167ge for better clarity. updated notes 2 , 3 , 4, 5 for better clarity. listed all product options in product portfolio . added typical values for i sb2 parameter. updated note 7 for better clarity. updated maximum ratings to extend limits for 5 v device. changed latch up current limit from 200 to 140 ma (per jedec limits). updated dc electrical characteristics corrected i oh and i ol conditions for v oh and v ol specifications. added i cc typical and maximum values at f = 1 mhz changed typical spec for i sb1 and i sb2 from 2.5 ? a to 3.2 ? a. split the i sb1 and i sb2 specs across multiple voltage ranges. updated description and test conditions for i sb1 and i sb2 parameters. added note 11 and referred it in the i sb1 and i sb2 parameters. changed c in and c out values from 8 pf to 10 pf. updated thermal resistance values of ? ja and ? jc parameters for 48 pin tsop i package. added values for v high parameters in ac test loads and waveforms . updated data retention characteristics split test conditions of i ccdr parameter into two rows to cover multiple v cc ranges. changed typical spec for i ccdr from 2.5 ? a to 3.2 ? a. updated note 15 to remove byte enables. updated data retention waveform (referred note 19 in figure 7 ). updated switching characteristics updated notes 20 , 23 for better clarity. updated switching waveforms updated note 25 for better clarity. updated figure 10 as a single figure applicable to both cy62167g and cy62167ge. referred notes 28 , 29 in figure 10 . referred note 28 in figure 11 . corrected typos in note 29 , 31 , 36 , 40 . referred note 34 in figure 12 .
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 25 of 28 *a (cont.) 3776318 aju 10/30/2012 removed ?write cycle no. 3 (we controlled, oe low)? waveform. removed the note ?during this period the i/os are in output state. do not apply input signals.? and its references. removed the note ?if ce goes high simultaneously with we going high, the output remains in a high-impedance state.? and its references (captured in notes 31 , 36 , 40 ) referred notes 38 , 39 , 40 in figure 13 . updated truth table ? cy62167g/cy62167ge (removed references of note 43 in bhe and ble column). updated package diagrams (spec 51-85150 (changed revision from *g to *h)). *b 4003550 memj 05/28/2013 updated document title to read as ?cy62167g/cy62167ge mobl ? , 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc)? added 55 ns (1.8 v) device details updated logic block diagram ? cy62167g . updated logic block diagram ? cy62167ge . updated pin configuration ? cy62167ge (added figure 4 ). updated product portfolio : updated details of i sb2 parameter. updated dc electrical characteristics : changed typical value of i cc parameter from 5 ma to 7 ma and max value from 30 to 36. changed typical value of i sb1 parameter from 3.2 a to 4 a for ?v cc = 1.65 to 2.2 v?. changed typical value of i sb2 parameter from 3.2 a to 4 a for ?v cc = 1.65 to 2.2 v?. updated ac test loads and waveforms : updated the table below figure 6 . updated data retention characteristics : changed typical value of i ccdr parameter from 3.2 a to 4 a for first condition only. updated i cc typical to 29 ma from 25 ma. updated data retention waveform : updated figure 7 . updated switching waveforms : updated figure 12 . renamed ?truth table ? cy62167g? as truth table ? cy62167g/cy62167ge and updated the same table (added byte information). updated ordering information (updated part numbers). document history page (continued) document title: cy62167g/cy62167ge mobl ? , 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc) document number: 001-81537 rev. ecn no. orig. of change submission date description of change
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 26 of 28 *c 4094068 nile / memj 10/29/2013 updated product portfolio : updated values of ?operating i cc ? at f = f max (corresponding to 55-ns speed bin only). replaced ?an error detection? with ?a single-bit error detection?. updated pin configuration ? cy62167g : updated title of figure 1 and figure 2 . updated pin configuration ? cy62167ge : updated title of figure 5 . updated dc electrical characteristics : referred note 8 in description of v ih parameter. updated test conditions of i cc parameter (removed f = f max and added f = 22.22 mhz (45 ns) and f = 18.18 mhz (55 ns) and added corresponding values). added typical and maximum values for i sb2 parameter fo r intermediate temperatures. updated data retention characteristics : added note 16 and referred the same note in i ccdr parameter. updated ordering information : updated part numbers. segregated 45 ns and 55 ns parts list in the table. updated ?package type? column (added err pin location information and single or dual chip enable information). added errata. updated in new template. *d 4274810 memj 02/08/2014 updated operating range : added note 9 and referred the same note in v cc column. *e 4292074 memj / vini 03/07/2014 updated dc electrical characteristics : changed i sb2 (max) at 25c from 7ua to 4.8ua changed i sb2 (typ) at 40c from 6ua to 4.5ua changed i sb2 (max) at 40c from 9ua to 8ua added note 10 and referred to typical values added note 24 and referred to write cycle timing parameters in switching characteristics referred note 31 to figure 10 . changed title of figure 11 from ?we controlled? to ?we controlled, oe low? added note 32 and 33 in figure 11 . added note 37 in figure 12 . added figure 14 , we controlled write corrected err table by replacing ?no error in stored data? with ?no single bit error in stored data?. corrected err pin location to e3 in 'dual chip enable with err option' in the 48-vfbga package in ordering information . added note 41 in figure 13 and figure 14 . *f 4330547 aju 04/02/2014 changed lower limit for v cc from 1.0 v to 1.2 v in i ccdr conditions. document history page (continued) document title: cy62167g/cy62167ge mobl ? , 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc) document number: 001-81537 rev. ecn no. orig. of change submission date description of change
preliminary cy62167g/cy62167ge mobl ? document number: 001-81537 rev. *i page 27 of 28 *g 4397546 vini 06/03/2014 updated features : changed typical standby current from 3.2 to 4.6 ?? a updated product portfolio : changed i sb1 and i sb2 typical from 4.0 to 5.5 ? a and maximum from 23.0 a to 26.0 a in the 1.8-v part changed 25 c i sb1 and i sb2 typical from 3.2 to 4.6 ? a and maximum from 4.8 a to 6.0 a in the 3.3-v and 5-v parts. changed 40 c i sb2 typical from 4.5 to 5.1 ? a in the 3.3-v and 5-v parts changed 70 c i sb2 typical from 9.0 to 8.4 ? a in the 3.3-v and 5-v parts. reworded foot notes 10, 12, and 14. referenced note 12 from max values of i sb2 at 25 c, 40c and 70 c updated data retention characteristics : changed iccdr typical current to 5.5 a and maximum to 26.0 a in the 1.8-v part changed iccdr typical current to 4.6 a in the 3.3-v and 5-v parts. *h 4489659 aju 09/01/2014 removed errata (the errata applicable for the rev. ** silicon only). added errata (the errata applicable for the rev. *c silicon only). *i 4469360 nile 09/18/2014 no technical updates. document history page (continued) document title: cy62167g/cy62167ge mobl ? , 16-mbit (1 m words 16 bit / 2 m words 8 bit) static ram with error-correcting code (ecc) document number: 001-81537 rev. ecn no. orig. of change submission date description of change
document number: 001-81537 rev. *i revised september 18, 2014 page 28 of 28 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oducts and company names mentioned in this document may be the trademarks of their respective holders. preliminary cy62167g/cy62167ge mobl ? ? cypress semiconductor corporation, 2012-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reaso nably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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